1. Field of the Invention
The present invention relates to a semiconductor layout design apparatus, a semiconductor layout design method and a computer readable medium which places macrocells in a placement region on a semiconductor substrate.
2. Related Art
In today's most LSI designs, many macrocells are used, which are typically placed manually by engineers. The placement of macrocells is performed after placing input/output elements and roughly placing blocks. After macrocells are placed, optimization of the placement is performed, which significantly changes the placement of the roughly placed blocks. Therefore, after the optimization of the placement, the placements of the blocks and macrocells must be adjusted again. Typically, this adjustment work is also manually performed by engineers. Thus, there is a problem that the qualities of eventual floor plans vary depending on the way to adjust (see Japanese Patent Laid-Open No. 06-244280 and No. 2006-190062).
Another problem with the conventional LSI design is that it takes long time before the final placement of macrocells is determined by the adjustment work, which leads to a high number of man-hours and costs for design.